1. Field
Example embodiments relate to semiconductor memory devices, and for example, to a parallel bit test circuit and/or method, which may solve a channel lack problem in a tester by reducing the number of output pins without increasing test time.
2. Description of Related Art
In a semiconductor memory device such as a Dynamic Random Access Memory (DRAM), data read and/or write operations should generally be performed with precision. In order to perform more precise data read and/or write operations fail cells should not exist within chips.
However, in a very highly integrated semiconductor memory device the number of cells integrated in one chip gradually increases and approaches tens of millions or more, and a possibility of an occurrence of fail cells may increase despite well-developed manufacturing processes. The fidelity of chips having fail cells may not be guaranteed unless a more precise test for chips is performed to sort out the chips including fail cells.
Issues in testing semiconductor memory devices may be largely classified into issues of the fidelity of the test and issues of test time. For example, issues of test time may be concerned with the cost of products. For example, issues of test time may be concerned with shortening a product development period of semiconductor memory devices, shortening a test time until a shipment of products, and/or improving an efficiency of production and/or a competition between manufacturers by performing testing at a higher speed for tens of thousands of cells so as to reduce the test time.
In general, if performing a test for each cell in order to sort out memory cells as a pass/fail within a semiconductor memory device, test time of a highly integrated or very highly integrated semiconductor memory device may be lengthened and/or a cost may increase.
Accordingly, a parallel bit test may be performed in order to reduce the test time.
In order to distinguish the pass/fail of chips of a wafer state, cell addresses processed as a fail in the chips may be decided in an Electro Die Sorting (EDS) step, and/or fail cells may be repaired. Accordingly, the parallel bit test may be useful.
For example, in the parallel bit test, the same data may be written to numerous cells and/or the data may be read by using an exclusive OR circuit. If the same data is read from the cells, a corresponding cell may be decided as a pass. If even one different data is read, a corresponding cell may be decided as a fail. Accordingly, the parallel bit test may shorten a test time.
A conventional parallel bit test will be described below referring to FIGS. 1 to 4.
FIG. 1 is a block diagram of a conventional parallel bit test circuit for use in a semiconductor memory device.
Referring to FIG. 1, the parallel bit test circuit may include a memory array 16 and a plurality of data compressors represented in FIG. 1 by data compressors 10 to 15. For example, the data compressors 10 to 15 in FIG. 1 may represent 16 data compressors of a parallel bit test circuit.
The memory array 16 may include a plurality of memory cells (not shown) arrayed in a matrix type. The plurality of memory cells may each be coupled to a corresponding data line.
The data compressors 10 to 15 may each include an exclusive OR circuit (XOR).
FIG. 2 provides an illustration of the data compressor 10 of FIG. 1 including the XOR circuit.
Referring to FIG. 2, if read data is applied to exclusive OR circuits 21 and 22 connected with data lines DL0, DL1, DL2 and DL3, the XOR 21 performs an XOR operation for data output from the data lines DL0 and DL2, and the XOR circuit 22 may perform an XOR operation for data output from the data lines DL1 and DL3. An OR circuit 23 receives an XOR operation result of the XOR circuits 21 and 22, and performs an OR operation. The OR circuit 23 outputs the result of the OR operation to an output pin DQ0. Data compressors 11 to 15 may be the same as the data compressor 10 in FIG. 2.
Referring back to FIG. 1, if one word line (not shown) is activated, data bits of 4×16 are read at once. The plurality of data lines coupled to each of the respective data compressors 10 to 15 may be four.
Accordingly, each of the data compressors 10 to 15 may compress data of 4 bits into 1 bit.
For example, if data is applied to data lines DL[3:0], if even one data is different therefrom, the data compressor 10 may output a logic ‘1’ to an output pin DQ0. If data applied to the data lines DL[3:0] are all the same, the data compressor 10 may output a logic ‘0’ to output pin DQ0.
If a burst length is 1, output pins used in the parallel bit test may be DQ0˜DQ15 as described above. However, if the burst length is 2, the number of output pins used in the parallel bit test may be reduced in half, though not shown in FIG. 1. For example, if the burst length is 2, output pins used in the parallel bit test may be DQ0, DQ2, DQ4, DQ6, DQ8, DQ10, DQ12 and DQ14.
The burst length may indicate the number of successive data within one clock cycle. For example, if a burst length is 1, data may be sampled only at a rising edge of clock signal, and if the burst length is 2, data may be sampled at a rising edge and a falling edge of the clock signal. For example, a burst length of 2 for a parallel bit test will be described below referring to FIG. 4.
FIG. 4 illustrates an example timing diagram provided if a burst length is 2. Referring to FIG. 4, if a read command READ is applied to a semiconductor memory device synchronized to a rising edge of clock signal CLK, data D1 may be output to an output pin DQ, and successive data D2 may be output to the output pin. For example, the data D1 may be output in response to the rising edge A1 of the clock signal CLK, and the data D2 may be output in response to a falling edge A2 of the clock signal CLK.
FIG. 3 is a block diagram for a parallel bit test provided if the size of a memory array increases by 50% by adding a parity cell area for an error correction to the memory array area of FIG. 1.
Referring to FIG. 3, the parallel bit test circuit may include data compressors 31 to 44 and output pins DQ0 to DQ23.
The data compressors 31 to 44 may be classified into two groups 30 and 40. A first group 30 may correspond to the data compressors shown in FIG. 1 and a second group 40 may be for data compressors for parity bits.
Bits not parity bits for error correction will be referred to as normal bits, the number of data lines coupled to a data compressor may be four and the number of data lines of the normal bit area may be 64. The number of data lines of the parity bit area may be 32. Accordingly, in this case a parity bit overhead may be 50%.
Accordingly, the number of the parity bit data compressors may be 8, and the number of the normal bit data compressors may be 16. The total number of data compressors may be 24.
As shown by reference number 48, a total of 96 data bits may be output simultaneously. Accordingly, in order to perform a parallel bit test with a burst length of 1 as shown by reference number 48, the number of output pins may be 24. As shown in a reference number 49, even for a burst length of 2, at least 16 output pins may be required.
Consequently, the number of chips simultaneously testable in one tester may be reduced, causing an increase in test time.
Accordingly, if a memory capacity increases, the number of input/output lines may increase, and parity bits for an error correction may be added.